Official PCIe 8.0 draft aims for 1 TB/s data rate

An official draft of the PCI Express (PCIe) 8.0 specification is out, targeting a blistering 1 terabyte per second when the kit finally hits the streets. The PCI Special Interest Group (PCI-SIG) has released draft 0.5 of the version 8.0 standard, incorporating feedback received from member organizations after the release of draft 0.3 last year. With an expected raw bit rate of 256 gigatransfers per second (GT/s) and up to 1 TB/s bi-directionally across a 16-lane configuration, PCIe 8.0 is set to deliver another doubling of bandwidth over its predecessor, something the engineers weren't sure could be done. PCI-SIG says the completed PCIe 8.0 specification remain on track for full release by 2028, though buyers may need to wait longer for any super-fast devices such as solid-state drives (SSDs). Micron, for example, announced mass production of what it claims is the first PCIe 6.0 SSD in February this year, four years after the standard was finalized. And with compatible CPUs from Intel and AMD not expected until later this year, there are only PCIe 5.0 systems available to plug them into. Hardware compatible with PCIe 7.0 (at 128 GT/s and 512 GB/s) is not scheduled to hit the shelves before 2027 at the earliest, and the first devices will likely be SSDs again. PCI-SIG says PCIe 8.0 is designed to meet the high-bandwidth, low-latency demands of data-hungry markets, including AI, datacenter infrastructure, high-speed networking, edge computing, and quantum computing. AI datacenters are dominated by proprietary tech, including Nvidia's NVLink, but PCI-SIG sees an opening for PCIe with Unordered I/O (UIO), an enhancement introduced in the PCIe 6.1 specification. Keeping pace, though, will demand that PCIe continues its cadence of doubling data rate with each generation. This likely means PCIe 8.0 won't target consumers when it arrives. As The Register previously pointed out, a single PCIe 4.0 x1 lane is sufficient for 10 GbE networking, while many consumer GPUs stick to four or eight lanes, since they don't really benefit from the additional bandwidth a full x16 slot would provide. The latest standard maintains the use of PAM4 (Pulse Amplitude Modulation with four levels) signaling and Flit-based encoding, introduced in PCIe 6.0. Flit stands for Flow Control Unit, which specifies a 256-byte packet with forward error correction (FEC) to provide low latency with high efficiency. ®